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Novel AI Hardware Architectures for Graph Processing

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About this talk

Description

What do graphs have to do with novel hardware architectures for AI workloads?

Graph processing is the key to unlocking new architectures, as much as new architectures can boost execution of graph-oriented workloads.

As machine learning-powered applications are proliferating, the workloads that are created in order to serve their requirements are taking up an ever increasing piece of the compute pie.

A recent IDC study found that Data Management, Application Development & Testing, and Data Analytics  workloads represented more than half of all IaaS and PaaS spending already in 2018. IDC notes that this was driven in part by initial adoption of artificial intelligence (AI) and machine learning (ML) capabilities.

As adoption grows, data and AI/ML workloads will dominate. This is why we see a renaissance of novel hardware architectures designed from the ground up to serve the needs of data and AI/ML workloads.

More specifically for data analytics, understanding relationships among data points is a challenging but essential capability. Graph analytics has emerged as an approach by which analysts can efficiently examine the structure of the large networks and draw conclusions from the observed patterns. This is why DARPA set out to develop a graph analytics processor with the HIVE Project.

Furthermore, all ML models are best expressed as graphs -- this is how ML libraries such as TensorFlow work. Efficient processing of graph-based networks involves large sparse data structures that consist of mostly zero values, and next generation architectures should avoid unnecessary processing.

This workshop aims to explore the interrelationship between graph processing and novel AI hardware architectures.

Key Topics

  • What are the characteristics of data and AI/ML workloads?
  • What types of architectures can effectively accommodate the needs imposed by these workloads?
  • Where does graph processing come into play, and how does it inform AI hardware architectures?
  • What types of architectures can effectively accommodate graph processing?

Target Audience

  • Machine Learning Practitioners
  • Data Scientists
  • CxOs
  • Investors

Goals

  • Explore the interplay between graph processing and novel AI hardware architectures
  • Answer questions that matter
    • How can those approaches complement one another, and what would that unlock?
    • What is the current state of the art, how and where is it used in the real world?
    • What are the next milestones / roadblocks?
    • Where are the opportunities for investment?

Session outline:

  • Introduction
    • Meet and Greet
    • Setting the stage
  • Data and AI/ML workloads
    • Background and growth trajectory
    • How are these workloads different from application workloads?
    • What kind of applications are these workloads generated by?
  • Hardware architectures for Data and AI/ML workloads
    • What are some of the issues legacy architectures face with data and AI/ML workloads?
    • What are some requirements for new hardware architectures for these workloads?
    • What is the current state of the art?
    • Who are some key players to keep an eye on?
  • Graph processing and AI hardware architectures
    • What is special about processing graphs?
    • What kind of problems can we solve with graphs?
    • How is graph processing relevant for AI hardware architectures?
    • Are there special requirements to serve graph processing workloads?
    • Where is graph processing used in production?
    • What is the current state of the art?
    • What are the major roadblocks / goals, how could we address them, and what would that enable?
    • What is the outlook?

Format

  • Extended panel
  • Expert discussion, coordinated by moderator
  • 2 hours running time
  • Running time includes modules of expert discussion, interspersed with modules of audience Q&A / interaction

Level

Intermediate - Advanced

Prerequisite Knowledge

  • Basic understanding of Data / Analytics / Graphs / Machine Learning / Deep Learning
  • Basic understanding of Hardware Architectures

You need an access pass to attend this session: Diversity Access Pass or Full Access Pass apply

Carlo Luschi

Carlo is responsible for the study and development of algorithms for machine intelligence. Prior to Graphcore, Carlo was a Member of Technical Staff at Bell Labs Research, Lucent Technologies, and more recently Director of Algorithms and Standards at Icera Inc., which was acquired by NVIDIA in 2011.

Tiernan Ray

Tiernan Ray has been covering technology & business for 27 years. He was most recently technology editor for Barron's where he wrote daily market coverage for the Tech Trader blog and wrote the weekly print column of that name. He has also worked for Bloomberg, SmartMoney, and for the prestigious ComputerLetter newsletter covering venture capital investments in tech

Evan Sparks

Evan Sparks, Vice President of Artificial Intelligence and High Performance Computing at HPE, co-founded Determined AI (now an HPE company). His group helps businesses get better AI-powered solutions to market faster and delivers the open source Determined Training Platform for large scale AI model development.

Val G. Cook

Val G. Cook is Chief Software Architect at Blaize. An AI visionary and authority on the design of graphics and visual computing architectures, Val possesses two decades of experience in graphics and multimedia algorithms and software architecture. He is responsible for the Blaize Graph Streaming Processor software programming environment.

Raghu Prabhakar

Raghu Prabhakar is a senior principal engineer and one of the founding engineers at AI innovation platform SambaNova Systems. His research interests are in the areas of programming models, compilers, and hardware architecture for reconfigurable dataflow architectures.

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